As designers strive to improve power, speed, and other Integrated Circuit (IC) capabilities, the number of input output (I/O) terminals that is used to connect ICs has also increased. Flip chip technology has become increasingly popular to provide improved connection capabilities.
Referring to FIG. 1, a flip chip 10 is a type of IC that does not require wire bonds. Instead, the chip 10 includes an array of bumps 12 over the core 13 of the chip and is placed on a substrate 14 with corresponding bonding pads 16. Solder beads are deposited on the bonding pads 16, and the chip 10 is mounted upside down in or on the substrate 14. The chip 10 and the substrate 14 are connected to each other after solder reflow. Underfill material is usually used to fill gaps between the chip 10 and the substrate 14.
Flip chip 10 design can be generally categorized as “package driven” or “chip driven” designs in package driven designs, a bump array is created, and the net associated to each bump is fixed. In chip driven design, I/O cells are either placed, or need to be placed, with constraints, and bump nets are assigned accordingly.
Referring to FIG. 2, one common flip-chip design is a peripheral I/O chip 20. In this design, an array 25 of bumps 22 located over the core area 24 of the chip 20. Input/Output (I/O) driver cells or I/O pads 26 (generally “pads”) for corresponding nets are located in I/O rows or legal locations for pad placement around the core 24. Connections 28 between bumps 22 and I/O pads 26 are made 28 using a redistribution layer (RDL) router. An I/O pad 26 that is connected to a bump 22 is illustrated as being a shaded I/O pad or rectangle 26, whereas an I/O pad or rectangle 26 that is not connected to a bump 22 is not shaded. An unshaded rectangle represents a legal site in which a pad can be assigned to an I/O row, but is currently vacant. Routing resources are typically limited to a single RDL layer. Consequently, placement of I/O pads 26 and assignment of nets to bumps 22 become critical since it may not be permissible to route connections 28 through multiple routing layers. Although known methods of making flip chip connections have been effective to send degree, they can be improved.
For example, referring to FIG. 3, placement may result in crossing 30 of connections 28 between a bump 22 and an I/O pad 26. Further, placement may result in congestion 32, or too many connections in one area, e.g. too many connections 28 between adjacent bumps 22. Consequently, a router may not have the required resources to complete the circuit connections. Further challenges involve creating the bump array 25 and assigning bumps 22 to corresponding nets, placing I/O pads 26 around the core 24 with respect to various placement constraints, and routing bumps 22 to I/O pads 26 while using only a single redistribution layer (RDL) through which the connections 28 between bumps 22 and pads 26 must be made. Routing problems can be even more complicated when working with large numbers of two-pin nets.
One known method of making flip chip connections is to manually assign nets, place pads and draw wires using design editors. Manual approaches, however, are labor intensive and time consuming. For example, a chip having 600-800 bumps can require at least one week for a skilled designer to place pads with possible constraints, assign bump nets, and manually perform routing layout. Designers sometimes have to settle for a less than optimum solution due to the large number of nets and long turnaround time. Further, designers may be required to use more than one layer to complete routing. These shortcomings limit the applicability and usefulness of manual methods.
Other known methods use design tools, such as CIOP, available from Cadence Design Systems, 2655 Seely Avenue, San Jose, Calif. 95134. These tools are improvements over manual methods, but have a number of shortcomings. For example, these tools involve manual editing for placement, bump net assignment and generation of a placement file. A user performs bump assignment and pad placement by writing the desired location/assignment into a spreadsheet file. CIOP reads in the spreadsheet file or circuit design, and a separate router is employed to complete routing. Thus, while CIOP and other tools have been successfully used in the past, they are semi-automatic and lack automated bump assignment and pad placement functionality. Instead, a user must create a test file to tell the tool the location of each bump/I/O pad, and to which net each bump should be connected. If the particular assignment creates crossing or congestion, the tool cannot automatically correct these errors. Rather, a user must manually modify the original design. Thus, known design tools are essentially manual placement tools with an automatic router and require substantial user input. Additionally, some known tools are based on a PCB design tool and lack functions that are important in IC design, such as snapping to manufacturing grid and wire splitting, e.g., to accommodate the max wire width rule.
Accordingly, there exists a need for a system and method that can manage bump assignment, pad placement and routing, while being able to adapt to different design styles, such as fixed bumps, fixed pads, irregular bump array, and multiple I/O rows. There is also a need for a system and method that can perform these functions within a single redistribution layer. There is also a need for an integrated system that includes all of this functionality.
Embodiments of the invention fulfill these unmet needs.